This description refers to embodiments of a semiconductor device having a gate and switch electrode and a method for switching a semiconductor device. In one embodiment, the present description pertains to power semiconductor devices such as IGBTs (Insulated Gate Bipolar Transistors) having a switch electrode and a gate electrode arranged in a trench structure, and to a method for switching such power semiconductor devices.
It is an ongoing desire in the development of power semiconductor devices to reduce the switching losses while maintaining the saturation voltage. In case of an IGBT, the saturation voltage is denoted by VCE,sat, wherein CE indicates the voltage between collector and emitter terminal.
Some attempts to reduce the switching losses of bipolar devices such as IGBTs include the integration of a p-channel field effect transistor parallel to the n-channel field effect transistor used for controlling the IGBT. In an on-state of the IGBT, the p-channel field effect transistor is blocked, i.e. it does not provide an electrical path between the drift region and the emitter terminal of the IGBT. Shortly before the n-channel field effect transistor is switched off to block the IGBT, the p-channel field effect transistor is switched on to provide a bypass through which the holes, which form the minority charge carriers, can flow to the emitter terminal. This reduces the charge stored in the drift region at low VCE and reduces switching losses.
Another approach includes formation of a plurality of trenches between which mesa structures having a small lateral width are arranged. The narrow width of the mesa structures causes a significant increase of minority charge carriers which reduces the saturation voltage VCE,sat.
For unipolar devices, for example power field effect transistors such as trench MOS-FETs, other approaches are used. For example, two electrodes can be formed in the trench, the upper one of which forms the gate electrode while the lower one is used as field electrode. Typically, the field electrode is clamped at source potential to reduce the gate-drain capacitance. In one embodiment, a voltage for generating an accumulation channel can be supplied to the field electrode. Moreover applying a suitable voltage for reducing the electric field over the oxide layer insulating the field and gate electrodes from the semiconductor substrate has also been suggested to allow reduction of the thickness of the oxide layer.